1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to a pipelined system and method for generating an area pattern for controlling various pixel operations within a graphics accelerator system.
2. Description of the Related Art
Early graphics systems were limited to two-dimensional (2D) graphics, were configured to compute a gray scale value for each pixel displayed, and acted as simple translators or interfaces to a display device. Modern high performance graphics systems, however, may support three-dimensional (3D) graphics with one or more special effects such as anti-aliasing, texturing, shading, fogging, alpha-blending, and specular highlighting. 3D graphics data may be several orders of magnitude larger than comparable 2D graphics data. 3D graphics data may include a set of information components for each vertex of the geometric primitives used to model the objects to be imaged.
In recent years, demand for high performance graphics systems that can render complex three-dimensional (3D) objects and scenes have increased substantially. This increase is at least in part due to the demand for new applications such as computer-generated animation for motion pictures, virtual reality simulators/trainers, and interactive computer games. These new applications place tremendous computational loads upon graphics systems. Modern computer displays have also improved and have a significantly higher pixel resolution, greater color depth, and are able to display more complex images with higher refresh rates than earlier models. Consequently, modern high performance graphics systems incorporate graphics processors with a great deal of complexity and power, and the color value of one pixel may be the accumulated result of many calculations involving several models and mathematical approximations.
With each new generation of graphics system, there is more image data to process, the processing is more complex, and there is less time in which to process it. Thus, there exists a continual need for more efficient graphical processing resources. In particular, there exists a significant need for circuits and processes capable of efficiently generating area patterns for pixels and/or supersamples.
A graphics system may generate blocks of data (such as pixels) and apply bits of an area pattern (stored in a memory) to the blocks. Area patterning in graphics systems has typically been implemented in a fashion that constrains block origin addresses to be aligned within the area pattern array. This is unfortunate because in certain circumstances it may be advantageous for rendering hardware and/or software to generate data blocks (e.g., blocks of pixels or supersamples) with addresses that are not necessarily aligned with respect to the area pattern array (or regularly demarked boundaries within the area pattern array). Thus, there exists a need for a circuit and corresponding methodology capable of mapping bits of an area pattern onto blocks having arbitrary origins with respect to the array pattern array.